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| www.irf.com 3jul09 ? 2009 international rectifier data sheet no. pd 60321a irs26302djpbf fully protected 3-phase bridge plus one gate driver features ? floating channel designed for bootstrap operation, fully ? operational to +600 v ? tolerant to negative transient voltage C dv/dt imm une ? full three phase gate driver plus one low side dri ver ? undervoltage lockout for all channels ? crossconduction prevention logic ? poweron reset ? integrated bootstrap diode for floating channel su pply ? over current protection on: dc(itrip), dc+(ground fault ), pfctrip/brtrip (pfc/brake protection). ? single pin fault diagnostic function ? diagnostic protocol to address fault register ? self biasing for ground fault detection high volta ge circuit ? 3.3 v logic compatible ? lower di/dt gate drive for better noise immunity ? externally programmable delay for automatic fault clear ? rohs compliant typical applications ? air conditioners inverters ? micro/mini inverter drives ? general purpose inverter ? motor control product summary topology 3 phase v offset 600 v v out 10 v C 20 v i o+ & i o (typical) 200 ma & 350 ma deadtime (typical) 290 ns package 44lead plcc typical connection diagram
irs26302dj www.irf.com ? 2009 international rectifier 2 table of contents page description 3 simplified block diagram 3 typical application diagram 4 qualification information 5 absolute maximum ratings 6 recommended operating conditions 7 static electrical characteristics 8 dynamic electrical characteristics 10 functional block diagram 12 input/output pin equivalent circuit diagram 13 lead definitions 14 lead assignments 15 application information and additional details 16 parameter temperature trends 36 package details 49 tape and reel details 50 part marking information 51 ordering information 52 irs26302dj www.irf.com ? 2009 international rectifier 3 description the irs26302djpbf are high voltage, high speed powe r mosfet and igbt drivers with three independent hi gh and low side referenced output channels for 3phase applications. an additional low side driver is inc luded for pfc or brake igbt driving operation. proprietary hvic t echnology enables rugged monolithic construction. l ogic inputs are compatible with cmos or lsttl outputs, down to 3.3v logic. three current trip functions that termi nate all seven outputs can be derived from three external sh unt resistors. each overcurrent trip functions cons ists of detecting excess current across a shunt resistor on dc+ bus, on dc bus and on brake or pfc circuitry. an enable function is available to terminate all outputs simu ltaneously and is provided through a bidirectional pin combined with an opendrain fault pin. fault signal is provi ded to indicate that an overcurrent or undervoltage shutdown has occurred. overcurrent fault conditions are clea red automatically after an externally programmed de lay via an rc network connected to the rcin input. a diagnosti c feature can give back to the controller the fault cause (uvcc, dc or dc overcurrent) and address a fault register. the output drivers feature a high pulse c urrent buffer stage. propagation delays are matched to simplify u se in high frequency applications designed for mini mum driver cross conduction. the floating channel can be used to drive nchannel power mosfets or igbts in the high side configuration which operates up to 600 v. simplified block diagram irs26302dj www.irf.com ? 2009 international rectifier 4 typical application diagram v cc hin (x3) rcin flt/en itrip v ss com lin (x3) lo (x 3) ho ( x 3) v b ( x3 ) v s (x 3) irs26302d v s1 v s2 v s 3 dc+ bus dc bus to load vdc gf vsdc pcfin/brin pcfout/brout pcftrip/brtrip ac main irs26302dj www.irf.com ? 2009 international rectifier 5 qualification information ? industrial ?? (per jedec jesd 47e) qualification level comments: this family of ics has passed jedecs industrial qualification. irs consumer qualificat ion level is granted by extension of the higher industrial level . moisture sensitivity level plcc44 msl3 ??? (per ipc/jedec jstd020c) machine model class b (per jedec standard jesd22a114d) human body model class 2 (per eia/jedec standard eia/jesd22a115a) esd charged device model class iv (per jedec standard jesd22c101c) ic latch-up test class i, level a (per jesd78a) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative for fu rther information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information. irs26302dj www.irf.com ? 2009 international rectifier 6 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all v oltage parameters are absolute voltages referenced to v ss unless otherwise stated in the table. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. voltage clamps a re included between v cc & com (25 v), v cc & v ss (20 v), and v b & v s (20 v). symbol definition min. max. units v b1,2,3 high side floating supply voltage 0.3 620 v ho1,2,3 high side floating output voltage v s1,2,3 0.3 v b1,2,3 + 0.3 v s1,2,3 high side offset voltage v b1,2,3 20 v b 1,2,3 + 0.3 vdc dcbus supply voltage 0.3 620 gf input voltage for ground fault detection vdc20 vdc+0.3 vsdc high voltage return for ground fault circuit v dc20 vdc+0.3 v cc low side and logic fixed supply voltage 0.3 20 ? com power ground v cc 25 v cc + 0.3 v lo1,2,3 low side output voltage lo1,2,3, pfcout 0.3 v cc + 0.3 v in input voltage lin1,2,3, hin1,2,3, itrip, pfctrip, flten, rcin 0.3 v cc + 0.3 v pfctrip /v brtrip input voltage v pfctrip /v brtrip 2 v cc + 0.3 v dv/dt allowable offset voltage slew rate 50 v/ns p d package power dissipation @ ta +25c 4.6 w r thja thermal resistance, junction to ambient 27 c/w t j junction temperature 150 t s storage temperature 55 150 t l lead temperature (soldering, 10 seconds) 300 c ? all supplies are fully tested at 25 v. an internal 20 v clamp exists for each supply. irs26302dj www.irf.com ? 2009 international rectifier 7 recommended operating conditions for proper operation, the device should be used wit hin the recommended conditions. all voltage parame ters are absolute voltages referenced to v ss unless otherwise stated in the table. the offset rating is tested with supplies of (v cc com) = (v b v s ) = 15 v. for proper operation the device should b e used within the recommended conditions. symbol definition min. max. units v b1,2,3 high side floating supply voltage v s1,2,3 + 10 v s1,2,3 + 20 v ho 1,2,3 high side output voltage ho1,2,3 v s1,2,3 v b1,2,3 v s 1,2,3 high side floating supply voltage ? vss C 8 600 v st 1,2,3 transient high side floating supply voltage ?? 50 600 vdc dcbus supply voltage (tbd) 600 gf input voltage for ground fault detection vdc5 v dc vsdc high voltage return for ground fault circuit v dc12 vdc11 v cc low side supply voltage 10 20 v lo1,2,3 low side output voltage lo1,2,3, pfcout 0 v cc com power ground 5 5 v scom negative transient vs voltage 0 20 1) v flt fault output voltage 0 v cc v rcin rcin input voltage 0 v cc v ho 1,2,3 high side output voltage v s1,2,3 v b1,2,3 v lo1,2,3 low side output voltage com v cc v itrip itrip input voltage 0 5 pfc itrip /br itrip pfc itrip /br itrip input voltage 2 0 v in logic input voltage lin, hin, pfcin, brin, en v ss v ss +5 v t a ambient temperature 40 125 oc ? logic operation for v s of C8 v to 600 v. logic state held for v s of C8 v to Cv bs . please refer to design tip dt973 for more details. ?? operational for transient negative v s of v ss 50 v with a 50 ns pulse width. guaranteed by design. ref er to the application information section of this datashe et for more details. irs26302dj www.irf.com ? 2009 international rectifier 8 static electrical characteristics (v cc com) = (v b v s ) = 15 v. ta = 25 c unless otherwise specified. the vin and iin parame ters are referenced to v ss and are applicable to all six channels. the vo and io parameters are referenced to respective v s and com and are applicable to the respective output lea ds ho or lo. the v ccuv parameters are referenced to v ss . the v bsuv parameters are referenced to v s . the pfcio/brio and vpfc/ vbr are referenced to v ss and are applicable to pfcout/brout lead. symbol definition min typ max units test conditions vih logic 1 input voltage 2.5 vil logic 0 input voltage 0.8 v in,th+ input positive going threshold 1.9 2.5 v in,th input negative going threshold 0.8 1 v it,th+ input positive going threshold 0.160 0.200 0.240 v it,th input negative going threshold 0.144 0.180 0.216 v v it,hys itrip hysteresis 20 mv v pfct,th+ v brt,th+ pfc/br positive going threshold 0.144 0.180 0.21 6 v pfct,th v brt,th pfc/br negative going threshold 0.160 0.200 0.24 0 v v pfct,hys v brt,hys pfc/br hysteresis 20 mv v gft,th+ gf positive going threshold 0.140 0.180 0.220 v gft,th gf negative going threshold 0.150 0.200 0.240 v v gft = v dc v gf v gft,hys gf hysteresis 20 mv v rcin,th+ rcin positive going threshold 8 v rcin,hys rcin hysteresis 3 v cc,uvth+ v cc supply undervoltage positive going threshold 10.2 11.1 12.0 v cc,uvth v cc supply undervoltage negative going threshold 10.0 10.9 11.8 v cc,uvhys v cc supply undervoltage hysteresis 0.2 v bs,uvth+ v bs supply undervoltage positive going threshold 10.2 11.1 12.0 v bs, uvth v bs supply undervoltage negative going threshold 10.0 10.9 11.8 v bs,uvhs v bs supply undervoltage hysteresis 0.2 v ilk offset supply leakage current 50 a vb1,2,3 = vdc = gf =600 v, vdc vdcs = 20 v iqbs quiescent vbs supply current 45 120 all inp ut/output in off status iqcc quiescent vcc supply current 2.5 4 ma all in put/output in off status io+ output high short circuit pulsed current, ho1,2,3 100 200 vout = 0 v, pw irs26302dj www.irf.com ? 2009 international rectifier 9 static electrical characteristics (continued) (v cc com) = (v b v s ) = 15 v. ta = 25 c unless otherwise specified. the vin and iin parame ters are referenced to v ss and are applicable to all six channels. the vo and io parameters are referenced to respective v s and com and are applicable to the respective output lea ds ho or lo. the v ccuv parameters are referenced to v ss . the v bsuv parameters are referenced to v s . the pfcio/brio and vpfc/ vbr are referenced to v ss and are applicable to pfcout/brout lead. symbol definition min typ max units test conditions pfci o+ / bri o+ output high short circuit pulsed current, pfc out /br out 120 250 p fcout = 0 v, pw irs26302dj www.irf.com ? 2009 international rectifier 10 dynamic electrical characteristics v cc = v b = 15 v, v s = v ss = com, t a = 25 c , and c l = 1000 pf unless otherwise specified. symbol definition min typ max units test conditions lo ton , ho ton turnon propagation delay, lo1,2,3, ho1,2,3 320 710 lin = 0 v 3.3 v , hin = 0 v lo toff , ho toff turnoff propagation delay, lo1,2,3, ho1,2,3 320 710 lin = 3.3 v 0 v, hin = 0 v lo tr , ho tr turnon rise time lo1,2,3, ho1,2,3 125 190 c load = 1nf lo tf ,ho tf turnoff fall time lo1,2,3, ho1,2,3 50 75 c load = 1nf p fcton /b rton turnon propagation delay, pfc out /br out (cl = 2200pf) 300 660 p fcin = 0 v 3.3 v p fctoff /b rtoff turnoff propagation delay, pfc out /br out (cl = 2200pf) 300 660 p fcin = 3.3 v 0 v p fctr /b rtr turnon rise time, pfc out /br out (cl= 2200 pf) 180 c load = 2.2 nf p fctf /b rtf turnoff rise time, pfc out /br out (cl = 2200 pf) 60 c load = 2.2 nf t en enable low to output shutdown propagation delay 350 460 650 v in, v en = 0 v or 3.3 v t itrip itrip to output shutdown propagation delay 800 v itrip = 2 v t itripbl itrip blanking time 250 400 600 v in = 0 v or 3.3 v v itrip = 2 v t pfctrip pfc trip to output shutdown propagation delay 800 t pfcbl /t brbl pfc trip /br trip blanking time 500 t filin input filter time ? (hin, lin, pfc in /br in , en) 200 350 v in = 0 v & 3.3 v t filteren enable input filter time 100 200 dt deadtime 190 290 420 lin = 3.3 v 0 v, hin = 0 v 3.3 v mt ton, off matching time (on all six channels) 50 mdt dt matching (hi>lo & lo>hi on all channels) 60 pm pulse width distortion ?? 75 ns pw input = 10 us t fltclr fault clear time rcin: r=2meg, c=1nf 40 60 80 s r = 100 k, c = 680 pf, on rcin t itripblk itrip blanking time 250 400 600 t itripflt itrip to fault time 800 1150 1500 v itrip = 0 v 2 v to flt/en = 3.3 v 0 v t itripout itrip to output shut down propagation delay 500 720 950 ns v itrip =0 v 2 v to lox/hox = 15 v 0 v ? the minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of t he input filter is exceeded. ?? pm is defined as pw in pw out . irs26302dj www.irf.com ? 2009 international rectifier 11 dynamic electrical characteristics v cc = v b = 15 v, v s = v ss = com, t a = 25 o c, and c l = 1000 pf unless otherwise specified. symbol definition min typ max units test conditions t itrippfc /t itri pbr itrip to pfcout/brout shutdown propagation delay 400 620 850 v itrip = -1 v 2 v to p fcout /b rout = 15 v 0 v t pfctripflt /t brtripflt pfctrip/brtrip to fault time 700 1000 1500 v pfctrip /v brtrip = 1v 1.5 v v to flt/en = 3.3 v 0 v t pfctripout /t brtripout pfctrip/brtrip to output shutdown propagation delay 400 600 950 v pfctrip /v brtrip = 1v 1.5 v to lox/hox = 15 v 0 v t pfctrippfc /t brtrippfc pfctrip/brtrip to pfc output shutdown propagation delay 320 500 850 v pfctrip /v brtrip = 1v 1.5 v to p fcout = 15 v 0 v t pfctripblk /t brtripblk pfctrip/brtrip blanking time 150 450 750 t gftripflt gftrip to fault time 1000 1400 1800 v gf = v dc v dc -1 v to flt/en = 15 v 0 v t gftripout gftrip to output shutdown propagation delay 700 1000 1300 v gf = v dc v dc -1 v to lox/hox = 15 v 0 v t gftrippfc gftrip to pfc output shutdown propagation delay 600 900 1200 v gf = v dc v dc -1 v to p fcout = 15 v 0 v t gftripblk gftrip blanking time 150 300 550 t enout en on to output propagation delay 300 400 500 v en = 0 v 3.3 v , linx/hinx = 3.3 v to lox/hox = 0 v 15 v t sdout en off to output shutdown propagation delay 320 440 560 v en = 3.3 v 0 v, linx/hinx = 3.3 v to lox/hox = 15 v 0 v t enpfc /t enb r en on to pfc/brake output propagation delay 200 320 500 v en = 0 v 3.3 v , p fcin /b rin = 3.3 v to p fcout /b rout = 0 v 15 v t sdpfc /t sdb r en off to output shutdown pfc/brake propagation delay 200 360 500 v en = 3.3 v 0 v, p fcin /b rin = 3.3 v to p fcout /b rout =15 v 0 v t handshake input to hand shake mode delay t diagin input to diag mode in delay t diagout input to diag mode out delay 300 500 700 ns see fault diagnostic state diagram note 1: a shootthrough prevention logic prevents lo1,2,3 and ho1,2,3 for each channel from turning on simult aneously. note 2 : u vcc is not latched, when v cc > u vcc , fault return to high impedance. note 3 : when itrip irs26302dj www.irf.com ? 2009 international rectifier 13 input/output pin equivalent circuit diagrams irs26302dj www.irf.com ? 2009 international rectifier 14 lead definitions symbol description v sdc gf supply return gf gf analog input for dc + overcurrent shutdown. when active, gf shuts down outputs and activates fault and rcin low. when gf becomes inac tive, fault stays active low for an externally set time t fltclr , then automatically becomes inactive (opendrain h igh impedance). v dc gf comparator supply (dc bus) hin1,2,3 logic inputs for high side gate driver outputs ( ho1,2,3), in phase lin1,2,3 logic input for low side gate driver outputs (lo1,2 ,3), in phase p fctrip/ /b rtrip analog input for pcf overcurrent shutdown. when act ive, gf shuts down outputs and activates fault and rcin low. when p fctrip/ /b rtrip becomes inactive, fault stays active low for an externally set time t fltclr , then automatically becomes inactive (opendrain h igh impedance). p fcout /b rout pfc/brake output p fcin /b rin input, pfc/brake, active high fault/en open drain and input, act high itrip analog input for dc C overcurrent shutdown. when active, itrip shuts down outputs and activates fault and rcin low. when itrip becomes inactive, fault stays active low for an externally set time t fltclr , then automatically becomes inactive (opendrain h igh impedance). rcin an external rc network input used to define the fau lt clear delay (t fltclr ) approximately equal to r*c. when rcin > 8 v, the fault pin goes back into an opendrain highimpedance state. v ss logic ground com power ground & analog input (itrip) lo1,2,3 low side driver outputs v cc low side supply voltage v s1,2,3 high voltage floating supply return ho1,2,3 high side driver outputs v b1,2,3 high side floating supply irs26302dj www.irf.com ? 2009 international rectifier 15 lead assignments irs26302dj www.irf.com ? 2009 international rectifier 16 application information and additional details information regarding the following topics are incl uded as subsections within this section of the data sheet. ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? shootthrough protection ? enable input ? fault reporting and programmable fault clear timer ? overcurrent protection ? overtemperature shutdown protection ? truth table: undervoltage lockout, itrip, and enab le ? diagnostics ? advanced input filter ? shortpulse / noise rejection ? integrated bootstrap functionality ? bootstrap power supply design ? separate logic and power grounds ? tolerant to negative v s transients ? pcb layout tips ? integrated bootstrap fet limitation ? additional documentation igbt/mosfet gate drive the irs26302dj hvics are designed to drive mosfet o r igbt power devices. figures 1 and 2 illustrate se veral parameters associated with the gate drive functiona lity of the hvic. the output current of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the highside power switch and v lo for the lowside power switch; this parameter is s ometimes generically called v out and in this case does not differentiate between th e highside or lowside output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + v s (or com) ho (or lo) v b (or v cc ) i o figure 1: hvic sourcing current figure 2: hvic sinking current irs26302dj www.irf.com ? 2009 international rectifier 17 switching and timing relationships the relationship between the input and output signa ls of the irs26302dj are illustrated below in figur es 3. from this figure, we can see the definitions of several timing parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. linx (or hinx) 50% 50% pw in pw out 10% 10% 90% 90% t off t on t r t f lox (or hox) figure 3: switching time waveforms the following two figures illustrate the timing rel ationships of some of the functionality of the irs2 6302dj; this functionality is described in further detail later in this document. during interval a of figure 5, the hvic has receive d the command to turnon both the high and lowsid e switches at the same time; as a result, the shootthrough prote ction of the hvic has prevented this condition and both the high and lowside output are held in the off state. interval b of figures 5 and 6 shows that the signal on the itrip, gf, pcftrip input pin has gone from a not active to an active state; as a result, all of the gate drive outputs have been disabled (i.e., see that hox has returned to the low state; lox is also held low), the voltage on the rc in pin has been pulled to 0 v, and a fault is repor ted by the fault output transitioning to the low state. once the it rip, gf, pcftrip input has returned to the not acti ve state, the output will remain disabled and the fault condition reported until the voltage on the rcin pin charges up to v rcin,th (see interval c in figure 6); the charging characte ristics are dictated by the rc network attached to the rcin pin. during intervals d and e of figure 5, we can see th at the enable (en) pin has been pulled low (as is t he case when the driver ic has received a command from the contr ol ic to shutdown); this results in the outputs (ho x and lox) being held in the low state until the enable pin is pulled high. irs26302dj www.irf.com ? 2009 international rectifier 18 flt/en itrip hin1,2,3 lin1,2,3 rcin ho1,2,3 lo1,2,3 gf, pcftrip pcfin pcfout a b c d e figure 4: input/output timing diagram 50% 90% 50% t fltclr t itrip t flt rcin itrip hox fault v rcin,th v it,th+ interval b interval c v it,th figure 5: detailed view of b & c intervals deadtime this family of hvics features integrated deadtime p rotection circuitry. the deadtime for these ics is fixed; other ics within irs hvic portfolio feature programmable dea dtime for greater design flexibility. the deadtime feature inserts a time period (a minimum deadtime) in which both th e high and lowside power switches are held off; t his is done to ensure that the power switch being turned off has f ully turned off before the second power switch is t urned on. this minimum deadtime is automatically inserter whenever the external deadtime is shorter than dt; external deadtimes larger than dt are not modified by the gate driver. figure 7 illustrates the deadtime period and the relationship between the output gate signals. the deadtime circuitry of the irs26302dj is matched with respect to the high and lowside outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. figure 7 defines the two deadtime parameters (i.e., dt 1 and dt 2 ) of a specific channel; the deadtime matching para meter (mdt) associated with the irs26302dj specifies the maximum difference between dt 1 and dt 2 . the mdt parameter also applies when comparing the dt of one channel of the irs26302dj t o that of another. irs26302dj www.irf.com ? 2009 international rectifier 19 figure 7: illustration of deadtime matched propagation delays the irs26302dj is designed with propagation delay m atching circuitry. with this feature, the ics res ponse at the output to a signal at the input requires approximat ely the same time duration (i.e., t on , t off ) for both the lowside channels and the highside channels; the maximum di fference is specified by the delay matching paramet er (mt). additionally, the propagation delay for each lowsi de channel is matched when compared to the other lo wside channels and the propagation delays of the highsid e channels are matched with each other; the mt spec ification applies as well. the propagation turnon delay (t on ) of the irs26302dj is matched to the propagation t urnon delay (t off ). input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the irs26302dj has been desi gned to be compatible with 3.3 v and 5 v logiclevel signal s. figure 8 illustrates an input signal to the irs2 6302dj, its input threshold values, and the logic state of the ic as a result of the input signal. figure 8: hin & lin input thresholds irs26302dj www.irf.com ? 2009 international rectifier 20 undervoltage lockout protection this family of ics provides undervoltage lockout pr otection on both the v cc (logic and lowside circuitry) power supply and the v bs (highside circuitry) power supply. figure 9 is u sed to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/ or v bsuv+/ ) the undervoltage protection is enabled or disabled. upon powerup, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turnon. additionally, if the v cc voltage decreases below the v ccuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition and shutdown the high and lowside gate drive outputs, and the fault pin will transit ion to the low state to inform the controller of the fault conditi on. upon powerup, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turnon. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition, and shutdown the highside gate drive ou tputs of the ic. the uvlo protection ensures that the ic drives the external power devices only when the gate supply vo ltage is sufficient to fully enhance the power devices. wit hout this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power s witch conducting current while the channel impedanc e is high; this could result in very high conduction losses within the power device and could lead to power device fai lure. figure 9: uvlo protection shoot-through protection the irs26302dj is equipped with shootthrough prote ction circuitry (also known as crossconduction pre vention circuitry). figure 10 shows how this protection ci rcuitry prevents both the high and lowside switch es from conducting at the same time. table 1 illustrates t he input/output relationship of the devices in the form of a truth table. note that the irs26302dj has noninverting inputs (the output is inphase with its respective input). irs26302dj www.irf.com ? 2009 international rectifier 21 figure 10: illustration of shoot-through protection circuitry hin lin ho lo 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 table 1: input/output truth table enable input the irs26302dj is equipped with an enable input pin that is used to shutdown or enable the hvic. when the en pin is in the high state the hvic is able to operat e normally (assuming no other fault conditions). w hen a condition occurs that should shutdown the hvic, the en pin sh ould see a low logic state. the enable circuitry o f the irs26302dj features an input filter; the minimum in put duration is specified by t filter,en . please refer to the en pin parameters v en,th+ , v en,th , and i en for the details of its use. table 2 gives a summa ry of this pins functionality and figure 11 illustrates the outputs response to a sh utdown command. enable input enable input high outputs enabled * enable input low outputs disabled table 2: enable functionality truth table (*assumes no other fault condition) irs26302dj www.irf.com ? 2009 international rectifier 22 figure 11: output enable/disable timing waveform fault reporting and programmable fault clear timer the irs26302dj provides an integrated fault reporti ng output and an adjustable fault clear timer. the re are several situations that would cause the hvic to report a fa ult via the fault pin: an undervoltage condition of v cc or itrip, ground fault (gf), pcftrip pin recognizes an overcu rrent. once the fault condition occurs, the fault pin is internally pulled to v ss and the fault clear timer is activated. the fault output stays in the low state until the fault condition has been removed and the fault clear time r expires; once the fault clear timer expires, the voltage on the fault pin will return to v cc . the length of the fault clear time period (t fltclr ) is determined by exponential charging characteris tics of the capacitor where the time constant is set by r rcin and c rcin . in figure 12 where we see that a fault condition has occurred (itrip), rcin and fault are pulled to v ss , and once the fault has been removed, the fault cl ear timer begins. figure 13 shows that r rcin is connected between the v cc and the rcin pin, while c rcin is placed between the rcin and v ss pins. figure 12: rcin and fault pin waveforms figure 13: programming the fault clear timer the design guidelines for this network are shown in table 3. c rcin 1 nf, ceramic 0.5 m to 2 m r rcin >> r on,rcin table 3: design guidelines irs26302dj www.irf.com ? 2009 international rectifier 23 the length of the fault clear time period can be de termined by using the formula below. v c (t) = v f (1e t/rc ) t fltclr = (r rcin c rcin )ln(1v rcin,th /v cc ) over-current protections the irs26302dj hvics are equipped with an itrip, gf and pfctrip input pin. these functionality can be used to detect overcurrent events in the dc bus, in the d c+ bus, in the pfc section and ground related. onc e the hvic detects an overcurrent event, the outputs are shut down, a fault is reported through the fault pin, an d rcin is pulled to v ss . the level of current at which the overcurrent prot ection is initiated is determined by the resistor n etwork (i.e., r 0 , r 1 , and r 2 ) connected to itrip as shown in figure 14, and the itrip threshold (v it,th+ ). the circuit designer will need to determine the maximum allowable level of current in the dc bus and select r 0 , r 1 , and r 2 such that the voltage at node v x reaches the overcurrent threshold (v it,th+ ) at that current level. v it,th+ = r 0 i dc (r 1 /(r 1 +r 2 )) figure 14: programming the over-current protection for example, a typical value for resistor r 0 could be 50 m. the voltage of the itrip pin shou ld not be allowed to exceed 5 v; if necessary, an external voltage clamp may be used. the shunt resistor or resistor network for gf or pc ftrip can be determined according to gf, pcftrip th reshold and level of protection current. the gf pin should not be outside this range (vdc+0.3v, vdc5v) and pcftri p should not be outside (vcc+0.3v, vss5v); if necessary, an ext ernal voltage clamp may be used. over-temperature shutdown protection the itrip input of the irs26302dj can also be used to detect overtemperature events in the system and initiate a shutdown of the hvic (and power switches) at that t ime. in order to use this functionality, the circu it designer will need to design the resistor network as shown in fig ure 15 and select the maximum allowable temperature . this network consists of a thermistor and two stand ard resistors r 3 and r 4 . as the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node v x . the resistor values should irs26302dj www.irf.com ? 2009 international rectifier 24 be selected such the voltage v x should reach the threshold voltage (v it,th+ ) of the itrip functionality by the time that the maximum allowable temperature is reached. the voltage of the itrip pin should not be allowed to e xceed 5 v. when using both the overcurrent protection and ov ertemperature protection with the itrip input, or ing diodes (e.g., dl4148) can be used. this network is shown in figure 16; the oring diodes have been labeled d 1 and d 2 . figure 15: programming over-temperature protection figure 16: using over-current protection and over- temperature protection truth table: undervoltage lockout, itrip, gf, pcftr ip and enable table 4 provides the truth table for the irs26302dj . the first line shows that the uvlo for v cc has been tripped; the fault output has gone low and the gate drive output s have been disabled. v ccuv is not latched in this case and when v cc is greater than v ccuv , the fault output returns to the high impedance st ate. the second case shows that the uvlo for v bs has been tripped and that the highside gate drive outputs have been disabled. after v bs exceeds the v bsuv threshold , ho will stay low until the hvic input receives a new rising transition of hin. the third case shows the normal operation of the hvic. the fourth case illustrates that the itrip trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been rep orted through the fault pin. same behavior if gf or pcftr ip threshold has been reached. in the last case, th e hvic has received a command through the en input to shutdown ; as a result, the gate drive outputs have been dis abled. vcc vbs itrip gf pfc trip en rcin fault lo ho pcfout uvlo v cc < v ccuv high 0 0 0 0 uvlo v bs 15 v < v bsuv 0 v 0 v 0 v 5 v high high z lin 0 0 normal operation 15 v 15 v 0 v 0 v 0 v 5 v high high z lin hin pcfin itrip fault 15 v 15 v >v itrip 0 v 0 v 5 v low 0 0 0 0 gf 15 v 15 v 0 v < gfth 0 v 5 v low 0 0 0 0 pcftrip 15 v 15 v 0 v 0 v irs26302dj www.irf.com ? 2009 international rectifier 26 set lin1=l, lin2,3=h;hinx=h wait t diagin flt/en = 0 itrip fault set lin2=l, lin1,3=h;hinx=h wait t diagin flt/en = 0 pfctrip fault yes no yes no set lin3=l, lin1,2=h;hinx=h wait t diagin gf fault flt/en = 0 no yes set lin3=l, lin1,2=h;hinx=h wait t diagin uvcc fault flt/en = 0 yes fault query start no exit fault query handshake mode figure 18: fault query procedure irs26302dj www.irf.com ? 2009 international rectifier 27 advanced input filter the advanced input filter allows an improvement in the input/output pulse symmetry of the hvic and hel ps to reject noise spikes and short pulses. this input filter h as been applied to the hin, lin, pfcin and en input s. the working principle of the new filter is shown in figures 19 and 20. figure 19 shows a typical input filter and the asym metry of the input and output. the upper pair of w aveforms (example 1) show an input signal with a duration mu ch longer then t fil,in ; the resulting output is approximately the difference between the input signal and t fil,in . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the differe nce between the input signal and t fil,in . figure 20 shows the advanced input filter and the s ymmetry between the input and output. the upper pa ir of waveforms (example 1) show an input signal with a d uration much longer then t fil,in ; the resulting output is approximately the same duration as the input signal . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the same du ration as the input signal. figure 19: typical input filter figure 20: advanced input filter short-pulse / noise rejection this devices input filter provides protection agai nst shortpulses (e.g., noise) on the input lines. if the duration of the input signal is less than t fil,in , the output will not change states. example 1 of figure 21 shows the input and output in the low state with positive noise spikes of duratio ns less than t fil,in ; the output does not change states. example 2 of figure 21 shows the input and output in the high st ate with negative noise spikes of durations less th an t fil,in ; the output does not change states. example 1 example 2 figure 21: noise rejecting input filters irs26302dj www.irf.com ? 2009 international rectifier 28 figures 22 and 23 present lab data that illustrates the characteristics of the input filters while rec eiving on and off pulses. the input filter characteristic is shown in figure 22; the left side illustrates the narrow pulse on ( short positive pulse) characteristic while the left shows the narrow puls e off (short negative pulse) characteristic. the x axis of figure 22 shows the duration of pw in , while the yaxis shows the resulting pw out duration. it can be seen that for a pw in duration less than t fil,in , that the resulting pw out duration is zero (e.g., the filter rejects the inp ut signal/noise). we also see that once the pw in duration exceed t fil,in , that the pw out durations mimic the pw in durations very well over this interval with the symmetry improving as the du ration increases. to ensure proper operation of th e hvic, it is suggested that the input pulse width for the highs ide inputs be 500 ns. the difference between the pw out and pw in signals of both the narrow on and narrow off cases is shown in figure 23; the careful reader will note the scale o f the yaxis. the xaxis of figure 21 shows the du ration of pw in , while the yaxis shows the resulting pw out Cpw in duration. this data illustrates the performance a nd near symmetry of this input filter. time (ns) figure 22: irs2336xd input filter characteristic figure 23: difference between the input pulse and t he output pulse irs26302dj www.irf.com ? 2009 international rectifier 29 integrated bootstrap functionality the irs26302dj features integrated highvoltage boo tstrap mosfets that eliminate the need of the exter nal bootstrap diodes and resistors in many applications . there is one bootstrap mosfet for each highside ou tput channel and it is connected between the v cc supply and its respective floating supply (i.e., v b1 , v b2 , v b3 ); see figure 24 for an illustration of this intern al connection. the integrated bootstrap mosfet is turned on only d uring the time when lo is high, and it has a limi ted source current due to r bs . the v bs voltage will be charged each cycle depending on th e ontime of lo and the value of the c bs capacitor, the drainsource (collectoremitter) dr op of the external igbt (or mosfet), and the lowsi de free wheeling diode drop. the bootstrap mosfet of each channel follows the st ate of the respective lowside output stage (i.e., the bootstrap mosfet is on when lo is high, it is off when lo is low), unless the v b voltage is higher than approximately 110% of v cc . in that case, the bootstrap mosfet is designed to remain off until v b returns below that threshold; this concept is illustrated in figure 25. v cc v b1 v b2 v b3 figure 24: internal bootstrap mosfet connection fig ure 25: bootstrap mosfet state diagram a bootstrap mosfet is suitable for most of the pwm modulation schemes and can be used either in parall el with the external bootstrap network (i.e., diode and resisto r) or as a replacement of it. the use of the integ rated bootstrap as a replacement of the external bootstrap network may have some limitations. an example of this limitati on may arise when this functionality is used in noncomplementar y pwm schemes (typically 6step modulations) and at very high pwm duty cycle. in these cases, superior performan ces can be achieved by using an external bootstrap diode in parallel with the internal bootstrap network. bootstrap power supply design for information related to the design of the bootst rap power supply while using the integrated bootstr ap functionality of the irs26302dj, please refer to application note 1123 (an1123) entitled bootstrap network analysi s: focusing on the integrated bootstrap functionality. this a pplication note is available at www.irf.com . for information related to the design of a standard bootstrap power supply (i.e., using an external di screte diode) please refer to design tip 044 (dt044) entitled using monolithic high voltage gate drivers. this design tip is available at www.irf.com . irs26302dj www.irf.com ? 2009 international rectifier 30 separate logic and power grounds the irs26302dj has separate logic and power ground pin (v ss and com respectively) to eliminate some of the noise problems that can occur in power conversion a pplications. current sensing shunts are commonly u sed in many applications for power inverter protection (i.e., o vercurrent protection), and in the case of motor d rive applications, for motor current measurements. in these situations, i t is often beneficial to separate the logic and pow er grounds. figure 26 shows a hvic with separate v ss and com pins and how these two grounds are used in the system. the v ss is used as the reference point for the logic and o vercurrent circuitry; v x in the figure is the voltage between the itrip pin and the v ss pin. alternatively, the com pin is the reference point for the lowside gate drive circuitry. the output voltage used to drive the lowside gate is v lo com; the gateemitter voltage (v ge ) of the lowside switch is the output voltage of the driver minus the drop across r g,lo . v s (x3) hvic ho (x3) v b (x3) lo (x3) com dc+ bus dc bus v cc d bs c bs v ss r g,lo r g,ho v s1 v s2 v s3 r 1 r 2 r 0 v ge1 + v ge2 + v ge3 + itrip v x + figure 26: separate v ss and com pins tolerant to negative v s transients a common problem in todays highpower switching co nverters is the transient response of the switch no des voltage as the power switches transition on and off quickly while carrying a large current. a typical 3phase inverter circuit is shown in figure 27; here we define the power switch es and diodes of the inverter. if the highside switch (e.g., the igbt q1 in figur es 28 and 29) switches off, while the u phase curre nt is flowing to an inductive load, a current commutation occurs fro m highside switch (q1) to the diode (d2) in parall el with the low side switch of the same inverter leg. at the same instance, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage. irs26302dj www.irf.com ? 2009 international rectifier 31 figure 27: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc bus figure 28: q1 conducting figure 29: d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 30 and 3 1), and q4 igbt switches on, the current commutation occurs fr om d3 to q4. at the same instance, the voltage node , v s2 , swings from the positive dc bus voltage to the nega tive dc bus voltage. figure 30: d3 conducting figure 31: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called negative v s transient. the circuit shown in figure 32 depicts one leg of t he three phase inverter; figures 33 and 34 show a s implified illustration of the commutation of the current betw een q1 and d2. the parasitic inductances in the pow er circuit from the die bonding to the pcb tracks are lumped togeth er in l c and l e for each igbt. when the highside switch is on, irs26302dj www.irf.com ? 2009 international rectifier 32 v s1 is below the dc+ voltage by the voltage drops asso ciated with the power switch and the parasitic elem ents of the circuit. when the highside power switch turns off , the load current momentarily flows in the lowsid e freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this cu rrent flows from the dc bus (which is connected to the com pin of the h vic) to the load and a negative voltage between v s1 and the dc bus is induced (i.e., the com pin of the hvic i s at a higher potential than the v s pin). figure 32: parasitic elements figure 33: v s positive figure 34: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 35 v/ns. the negat ive v s transient voltage can exceed this range during some events su ch as short circuit and overcurrent shutdown, when di/dt is greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. the irs26302dj has been seen to with stand large negative v s transient conditions on the order of 50 v for a period of 50 ns. an illustration of the ir s26302djs performance can be seen in figure 35. t his experiment was conducted using various loads to create this co ndition; the curve shown in this figure illustrates the successful operation of the irs26302dj under these stressful c onditions. in case of v s transients greater then 20 v for a period of time greater than 100 ns; the hvic is des igned to hold the highside outputs in the off stat e for 4.5 s in order to ensure that the high and lowside power s witches are not on at the same time. figure 35: negative v s transient results for an international rectifier h vic even though the irs26302dj has been shown able to h andle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use. irs26302dj www.irf.com ? 2009 international rectifier 33 pcb layout tips distance between high and low voltage components: its strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. the irs26302dj in the plcc44 package has had some unused pins removed in order to maximize the distance between the high vol tage and low voltage pins. please see the case outline plcc44 information in this datasheet for the detai ls. ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 36). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, curr ent can be injected inside the gate drive loop via the igbt collectortogate parasitic capacitance. the parasi tic autoinductance of the gate loop contributes to developing a voltage across the gateemitter, thus increasing th e possibility of a self turnon effect. figure 36: antenna loops supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and v ss pins. this connection is shown in figure 37. a ceramic 1 f c eramic capacitor is suitable for most applications. this component should be placed as close as possible to the pins in order to reduce parasitic elements. figure 37: supply capacitor irs26302dj www.irf.com ? 2009 international rectifier 34 routing and placement: power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the pha se voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the highside emitter to lowside collector distance, and 2) minimize th e lowside emitter to negative bus rail stray inductance. how ever, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. this includes pl acing a resistor (5 or less) between the v s pin and the switch node (see figure 36), and in some cases using a cla mping diode between v ss and v s (see figure 39). see dt044 at www.irf.com for more detailed information. figure 38: v s resistor figure 39: v s clamping diode integrated bootstrap fet limitation the integrated bootstrap fet functionality has an o perational limitation under the following bias cond itions applied to the hvic: ? vcc pin voltage = 0v and ? vs or vb pin voltage > 0 in the absence of a vcc bias, the integrated bootst rap fet voltage blocking capability is compromised and a current conduction path is created between vcc & vb pins, as illustrated in fig.40 below, resulting in power loss and possible damage to the hvic. figure 40: current conduction path between vcc and vb pin irs26302dj www.irf.com ? 2009 international rectifier 35 relevant application situations: the above mentioned bias condition may be encounter ed under the following situations: ? in a motor control application, a permanent magnet motor naturally rotating while vcc power is off. in this condition, back emf is generated at a motor terminal which causes high voltage bias on vs nodes resulting unwanted current flow to vcc. ? potential situations in other applications where v s/vb node voltage potential increases before the vcc voltage is available (for example due to sequen cing delays in smps supplying vcc bias) application workaround: insertion of a standard pn junction diode between vcc pin of ic and positive terminal of vcc capacito rs (as illustrated in fig.41) prevents current conduction outof vcc pin of gate driver ic. it is important not to connect the vcc capacitor directly to pin of ic. diode sele ction is based on 25v rating or above & current cap ability aligned to icc consumption of ic 100ma should cov er most application situations. as an example, part number # ll4154 from diodes inc (25v/150ma standard diode) can be used. figure 41: diode insertion between vcc pin and vcc capacitor note that the forward voltage drop on the diode ( v f ) must be taken into account when biasing the vcc p in of the ic to meet uvlo requirements. vcc pin bias = vcc supply voltage C v f of diode . additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these docum ents. dt973: managing transients in control ic driven po wer stages an1123: bootstrap network analysis: focusing on th e integrated bootstrap functionality dt044: using monolithic high voltage gate drivers an978: hv floating mosgate driver ics vcc vss (or com) vb vcc capacitor vcc vss (or com) vb vcc capacitor irs26302dj www.irf.com ? 2009 international rectifier 36 parameter temperature trends figures 42117 provide information on the experimen tal performance of the irs26302dj hvic. the line plotted in each figure is generated from actual lab data. a large number of individual samples were te sted at three temperatures (40 oc, 25 oc, and 125 oc) in o rder to generate the experimental (exp.) curve. th e line labeled exp. consist of three data points (one data point at each of the tested temperatures) that hav e been connected together to illustrate the understood tre nd. the individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 0.0 2.1 4.2 6.3 8.4 10.5 50 25 0 25 50 75 100 125 temperature ( o c) llk (ua) exp. fig. 42. offset supply leakage current vs. temper ature fig. 43. input bias current vs. temperature fig. 45. rcin input bias current vs. temperature 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 50 25 0 25 50 75 100 125 temperature ( o c) lin (ua) exp. 0.01 0.00 0.01 0.02 0.03 0.04 0.05 50 25 0 25 50 75 100 125 temperature ( o c) ircin (ua) exp. 0.00 300.00 600.00 900.00 1200.00 1500.00 50 25 0 25 50 75 100 125 temperature (oc) lin+ (ua) exp . fig. 44. input bias current vs. temperature irs26302dj www.irf.com ? 2009 international rectifier 37 fig. 46. pfc trip input bias current vs. temperature fig. 49. itrip input bias current vs. temperature fig. 47. pfc trip input bias current vs. temperature fig. 50. quiescent v cc supply current vs. temperature fig. 51. quiescent v bs supply current vs. temperature 0.00 5.10 10.20 15.30 20.40 25.50 30.60 50 25 0 25 50 75 100 125 temperature ( o c) ipfctrip+ (ua) exp. 0.00 0.40 0.80 1.20 1.60 2.00 50 25 0 25 50 75 100 125 temperature ( o c) iitrip+ (ua) exp. 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 50 25 0 25 50 75 100 125 temperature ( o c) ipfctrip (ua) exp. 0.00 1.25 2.50 3.75 5.00 50 25 0 25 50 75 100 125 temperature ( o c) iqcc (ma) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) iqbs (ua) exp. 0.00 0.01 0.02 0.03 0.04 0.05 0.06 50 25 0 25 50 75 100 125 temperature ( o c) iitrip (ua) exp. fig. 48. itrip input bias current vs. temperature irs26302dj www.irf.com ? 2009 international rectifier 38 fig. 52. turnon propagation delay vs. temperature fig. 53. turnoff propagation delay vs. temperature fig. 54. turnon rise time vs. temperature fig. 55. turnoff fall time vs. temperature fig. 56. turnon propagation delay vs. temperature fig. 57. turnoff propagation delay vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) loton (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) lotoff (ns) exp. 0 50 100 150 200 50 25 0 25 50 75 100 125 temperature ( o c) lotr (ns) exp. 0 10 20 30 40 50 60 70 50 25 0 25 50 75 100 125 temperature ( o c) lotoff (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) hoton (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) hotoff (ns) exp. irs26302dj www.irf.com ? 2009 international rectifier 39 fig. 58. turnon rise time vs. temperature fig. 59. turnoff fall time vs. temperature fig. 60. turnon propagation delay vs. temperature fig. 61. turnoff propagation delay vs. temperature fig. 62. turnon rise time vs. temperature fig. 63. turnoff fall time vs. temperature 0 40 80 120 160 200 50 25 0 25 50 75 100 125 temperature ( o c) hotr (ns) exp. 0 10 20 30 40 50 60 50 25 0 25 50 75 100 125 temperature ( o c) hotff (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) pfcton (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) pfctoff (ns) exp. 0 50 100 150 200 250 300 50 25 0 25 50 75 100 125 temperature ( o c) pfctr (ns) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) pfctf (ns) exp. irs26302dj www.irf.com ? 2009 international rectifier 40 fig. 64. deadtime rise time vs. temperature fig. 65. ton, off matching time vs. temperature fig. 66. deadtime matching vs. temperature fig. 67. pulse width distortion vs. temperature fig. 68. input filter time vs. temperature fig. 69. itrip to fault time vs. temperature 0 150 300 450 600 50 25 0 25 50 75 100 125 temperature ( o c) dt (ns) exp. 0 10 20 30 40 50 50 25 0 25 50 75 100 125 temperature ( o c) mt (ns) exp. 0 10 20 30 40 50 50 25 0 25 50 75 100 125 temperature ( o c) mdt(ns) exp. 0 10 20 30 40 50 50 25 0 25 50 75 100 125 temperature ( o c) pm (ns) exp. 0 100 200 300 400 500 600 50 25 0 25 50 75 100 125 temperature ( o c) tfilin (ns) exp. 0 400 800 1200 1600 2000 50 25 0 25 50 75 100 125 temperature ( o c) titripflt (ns) exp. irs26302dj www.irf.com ? 2009 international rectifier 41 fig. 70. itrip to output shutdown propagation delay vs. temperature fig. 71. itrip to pfc out shutdown propagation delay vs. temperature fig. 72. fault clear time rcin vs. temperature fig. 73. itrip blanking time vs. temperature fig. 74. pfc trip to fault time vs. temperature fig. 75. pfc trip to output shutdown propagation delay vs. temperature 0 250 500 750 1000 1250 1500 50 25 0 25 50 75 100 125 temperature ( o c) titripout (ns) exp. 0 250 500 750 1000 1250 1500 50 25 0 25 50 75 100 125 temperature ( o c) titrippfc (ns) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) tfltclr (us) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) titripblk (ns) exp. 0 400 800 1200 1600 2000 50 25 0 25 50 75 100 125 temperature ( o c) tpfctripflt (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tpfctripout (ns) exp. irs26302dj www.irf.com ? 2009 international rectifier 42 fig. 76. pfc trip to pfc output shutdown propagation delay vs. temperature fig. 77. fault clear time rcin vs. temperature fig. 78. pfc trip blanking time vs. temperature fig. 79. gf trip to fault time vs. temperature fig. 80. gf trip to output shutdown propagation delay vs. temperature fig. 81. gf trip to pfc output shutdown propagation delay vs. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tpfctrippfc (ns) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) tfltclr (us) exp. 0 150 300 450 600 750 50 25 0 25 50 75 100 125 temperature ( o c) tpfctripblk (ns) exp. 0 500 1000 1500 2000 2500 50 25 0 25 50 75 100 125 temperature ( o c) tgftripflt (ns) exp. 0 500 1000 1500 2000 2500 50 25 0 25 50 75 100 125 temperature ( o c) tgftripout (ns) exp. 0 500 1000 1500 2000 2500 50 25 0 25 50 75 100 125 temperature ( o c) tgftrippfc (ns) exp. irs26302dj www.irf.com ? 2009 international rectifier 43 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tgftripblk (ns) exp. fig. 82. gf trip blanking time vs. temperature fig. 83. en on to output propagation delay vs. tempe rature fig. 84. en off to output shutdown propagation delay vs. temperature fig. 85. enable input filter time vs. temperature fig. 86. en on to pfc output propagation delay vs. temperature fig. 87. en off to output shutdown pfc propagation del ay vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tenout (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tsdout (ns) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) tfilteren (ns) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) tenpfc (ns) exp. 0 150 300 450 600 750 50 25 0 25 50 75 100 125 temperature ( o c) tsdpfc (ns) exp. irs26302dj www.irf.com ? 2009 international rectifier 44 fig. 88. input to hand shake mode delay vs. temperature fig. 89. input to diag mode in delay vs. temperature fig. 90. input to diag mode out delay vs. temperature fig. 91. output high short circuit pulsed current pfc out vs. temperature fig. 92. output high short circuit pulsed current, ho1,2,3 vs. temperature fig. 93. output low short circuit pulsed current, ho1,2,3 vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tnandshake (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tdiagin (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) tdiagout (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) pfcio+ (ma) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) io+ (ma) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) io (ma) exp. irs26302dj www.irf.com ? 2009 international rectifier 45 fig. 94. output low short circuit pulsed current, pfc out vs. temperature fig. 95. rcin low on resistance vs. temperature fig. 96. flt low on resistance vs. temperature fig. 97. input negative going threshold vs. temperature fig. 98. input positive going threshold vs. temperature fig. 99. input negative going threshold vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) pfcio (ma) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) ron_rcin (ohm) exp. 0.00 0.50 1.00 1.50 2.00 2.50 50 25 0 25 50 75 100 125 temperature (oc) vin,th (v) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature (oc) ron_flt (ohm) exp. 0.00 0.50 1.00 1.50 2.00 2.50 3.00 50 25 0 25 50 75 100 125 temperature (oc) vin,th+ (v) exp. 0.00 0.10 0.20 0.30 0.40 0.50 50 25 0 25 50 75 100 125 temperature (oc) vitrip,th (v) exp. irs26302dj www.irf.com ? 2009 international rectifier 46 fig. 100. input positive going threshold vs. temperature fig. 101. pfc negative going threshold vs. temperature fig. 102. pfc positive going threshold vs. temperature fig. 103. gf negative going threshold vs. temperature fig. 104. gf positive going threshold vs. temperature fig. 105. rcin positive going threshold vs. temperature 0.00 0.10 0.20 0.30 0.40 0.50 50 25 0 25 50 75 100 125 temperature (oc) vitrip,th+ (v) exp. 0.00 0.10 0.20 0.30 0.40 0.50 50 25 0 25 50 75 100 125 temperature (oc) vpfctrip,th (v) exp. 0.00 0.10 0.20 0.30 0.40 0.50 50 25 0 25 50 75 100 125 temperature (oc) vpfctrip,th+ (v) exp. 0.00 0.10 0.20 0.30 0.40 0.50 50 25 0 25 50 75 100 125 temperature (oc) vgf,th (v) exp. 0.00 0.10 0.20 0.30 0.40 0.50 50 25 0 25 50 75 100 125 temperature (oc) vgf,th+ (v) exp. 0.00 3.00 6.00 9.00 12.00 15.00 50 25 0 25 50 75 100 125 temperature (oc) vrcin,th+ (v) exp. irs26302dj www.irf.com ? 2009 international rectifier 47 fig. 106. v cc supply undervoltage negative going threshold vs. temperature fig. 107. v cc supply undervoltage positive going threshold vs. temperature fig. 108. v cc supply undervoltage hysteresis vs. temperature fig. 110. v bs supply undervoltage negative going threshold vs. temperature fig. 111. v bs supply undervoltage positive going threshold vs. temperature 0.00 4.00 8.00 12.00 16.00 20.00 50 25 0 25 50 75 100 125 temperature (oc) vcc,uvth (v) exp. 0.00 4.00 8.00 12.00 16.00 20.00 50 25 0 25 50 75 100 125 temperature (oc) vcc,uvth+ (v) exp. 0.00 0.10 0.20 0.30 0.40 0.50 50 25 0 25 50 75 100 125 temperature (oc) vcc,uvhys (v) exp. 0.00 5.00 10.00 15.00 20.00 25.00 50 25 0 25 50 75 100 125 temperature (oc) vbs,uvth (v) exp. 0.00 5.00 10.00 15.00 20.00 25.00 50 25 0 25 50 75 100 125 temperature (oc) vbs,uvth+ (v) exp. 0.00 0.10 0.20 0.30 0.40 50 25 0 25 50 75 100 125 temperature (oc) vbs,uvhys (v) exp. fig. 109. v bs supply undervoltage hysteresis vs. temperature irs26302dj www.irf.com ? 2009 international rectifier 48 fig. 112. low level output voltage, v bias v o , pfc out vs. temperature fig. 114. low level output voltage, v o , ho1,2,3 vs. temperature fig. 113. high level output voltage, v bias v o , pfc out vs. temperature fig. 115. high level output voltage, v bias v o , ho1,2,3 vs. temperature fig. 116. ron internal bootstrap diode vs. temperature 0.00 50.00 100.00 150.00 200.00 250.00 50 25 0 25 50 75 100 125 temperature (oc) vpfcl (mv) exp. 0.00 100.00 200.00 300.00 400.00 500.00 50 25 0 25 50 75 100 125 temperature (oc) vol (mv) exp. 0.00 200.00 400.00 600.00 800.00 1000.00 50 25 0 25 50 75 100 125 temperature (oc) vpfch (mv) exp. 0.00 350.00 700.00 1050.00 1400.00 1750.00 50 25 0 25 50 75 100 125 temperature (oc) voh (mv) exp. 0.00 175.00 350.00 525.00 700.00 50 25 0 25 50 75 100 125 temperature (oc) rbs (ohm) exp. 0.00 0.01 0.02 0.03 0.04 0.05 50 25 0 25 50 75 100 125 temperature ( o c) ienin (ua) exp. fig. 117. en input bias current vs. temperature irs26302dj www.irf.com ? 2009 international rectifier 49 package details: plcc44 irs26302dj www.irf.com ? 2009 international rectifier 50 tape and reel details: plcc44 carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c irs26302dj www.irf.com ? 2009 international rectifier 51 part marking information irs26302dj www.irf.com ? 2009 international rectifier 52 ordering information standard pack base part number package type form quantity complete part number tube/bulk 27 irs26302djpbf irs26302dj plcc44 tape and reel 500 irs26302djtrpbf the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of this information . international rectifier assumes no responsibilit y for any infringement of patents or of other rights of third parties which may result from the use of this information. no license is grante d by implication or otherwise under any patent or patent rights of international rectifier. the specifications mentioned in this document are subject to change without notice. this document supersedes and replaces all information pr eviously supplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technicalinfo/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 2527105 irs26302dj www.irf.com ? 2009 international rectifier 53 revision history date comment mm/dd/yy original document rev3.1 started from rev3.0 of repository: header and foote r updated, standard package plcc44 specified , duplicate definition in dynamic electrical characte ristic deleted rev3.3 add application part related to bootstrap fe t limitation |
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